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參數(shù)資料
| 型號： | SSD1852T2R1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver With Controller CMOS |
| 中文描述： | LCD段/與普通的CMOS驅(qū)動器控制器 |
| 文件頁數(shù)： | 16/55頁 |
| 文件大?。?/td> | 637K |
| 代理商： | SSD1852T2R1 |
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SSD1852
Rev 1.0
01/2003
SOLOMON
11
7
FUNCTIONAL BLOCK DESCRIPTIONS
7.1
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data
is directed to this module based upon the input of the
D/C
pin. If
D/C
is high, data is written to
Graphic Display Data RAM (GDDRAM). If
D/C
is low, the input at D
0
-D
7
is interpreted as a
Command and it will be decoded and written to the corresponding command register.
Reset is of the same function as Power ON Reset (POR). Once
RES
receives a negative reset
pulse of about 10us, all internal circuitry will be back to its initial status. Refer to Command
Description section for more information.
7.2
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
0
-D
7
),
R/
W
(
WR
)
,
D/C
,
E(
RD
)
and
CS
.
R/
W
(
WR
)
input High indicates a read operation from the Graphic Display Data
RAM (GDDRAM) or the status register.
R/
W
(
WR
)
input Low indicates a write operation to
Display Data RAM or Internal Command Registers depending on the status of
D/C
input. The
E(
RD
)
and
CS
input serves as data latch signal (clock) when they are high and low
respectively. Refer to Figure 15 of parallel timing characteristics for Parallel Interface Timing
Diagram of 6800-series microprocessors for details.
In order to match the operating frequency of display RAM with that of the microprocessor,
pipeline processing is internally performed which requires the insertion of a dummy read before
the first actual display data read. This is shown in Figure 3.
7.3
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D
0
-D
7
),
R/
W
(
WR
)
,
E(
RD
)
,
D/C
and
CS
. The
CS
input serves as data latch signal (clock) when it is low.
D/C
determines
the D
0
~D
7
a display data or status register read.
WR
and
RD
inputs indicate a write or read
cycle when
CS
is low. Refer to Figure 16 of parallel timing characteristics for Parallel Interface
Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display
data read.
7.4
MPU Serial 4-wire Interface
The serial interface consists of serial clock SCK, serial data SDA,
D/C
and
CS
. SDA is
shifted into an 8-bit shift register on every rising edge of SCK in the order of D
7
, D
6
,... D
0
.
D/C
is
sampled on every eighth clock cycles and the data byte in the shift register is written to the
Display Data RAM or command register in the same clock cycle. No extra clock cycle or
command is required to end the transmission.
7.5
MPU Serial 3-wire Interface
Operation is similar to 4-wire serial interface while
D/C
is not been used. The Set Display
Data Length command is used to indicate a specified number display data byte (1-256) to be
transmitted. Next byte after the display data string is handled as a command.
It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in
the serial communication, a hardware reset pulse at
RES
pin is required to initialize the chip for
re-synchronization.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSD1852TR1 | LCD Segment / Common Driver With Controller CMOS |
| SSD1852Z | LCD Segment / Common Driver With Controller CMOS |
| SSD1854U | LCD Segment / Common Driver with Controller CMOS |
| SSD1854Z | LCD Segment / Common Driver with Controller CMOS |
| SSD1854 | LCD Segment / Common Driver with Controller CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSD1852TR1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver With Controller CMOS |
| SSD1852Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver With Controller CMOS |
| SSD1854 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1854U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
| SSD1854Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
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