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參數(shù)資料
| 型號： | SSD1818A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller |
| 中文描述： | LCD段/驅(qū)動器與控制器通用 |
| 文件頁數(shù)： | 19/47頁 |
| 文件大?。?/td> | 642K |
| 代理商： | SSD1818A |
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SSD1818A
Rev 1.2
P 19/47 Mar 2004
Solomon Systech
SSD1815B
SSD1818A
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
R3
R1
R2
R4
+
V
DD
C5
+
C4
+
C3
+
C2
+
C1
Remark: 1. C1 ~ C5 = 0.01 ~ 0.47uF
2. R1 ~ R4 = 100k~ 1M
4. Bias Ratio Selection circuitry
The bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9.
Since there will be slightly different in command pattern for different MUX, please refer to Command
Descriptions section of this data sheet. If the output op-amp buffer option in Set Power Control Register
command is enabled, this circuit block will divide the regulator output (V
L6
) to give the LCD driving levels
(V
L2
~ V
L5
). A low power consumption circuit design in this bias divider saves most of the display current
comparing to the traditional design. Stabilizing Capacitors (0.1uF ~ 0.47uF) are required to be connected
between these voltage level pins (V
L2
~ V
L5
) and (V
DD
). If the LCD panel loading is heavy, four additional
resistors are suggested to add to the application circuit as follows:
5. Self adjust temperature compensation circuitry
This block provides 4 different compensation settings to satisfy various liquid crystal temperature grades
by software control. Default temperature coefficient (TC) setting is TC0.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
104 x 65 = 6760 bits. Table 4 on Page 20 is a description of the GDDRAM address map.
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display. Table 4 on Page 20 shows the case in which the
display start line register is set to 38h.
For those GDDRAM out of the display common range, they could still be accessed, for either preparation
of vertical scrolling data or even for the system usage.
~1M
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| SSD1818ATR1 | LCD Segment / Common Driver with Controller |
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| SSD1818ATR1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller |
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| SSD1820ATR1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller CMOS |
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