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參數(shù)資料
| 型號： | SSD1800 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller |
| 中文描述： | LCD段/驅(qū)動器與控制器通用 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 598K |
| 代理商： | SSD1800 |
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Solomon Systech
Mar 2004
P 12/42 Rev 1.0
SSD1800 Series
7
PIN DESCRIPTIONS
7.1 D/
C
This pin is Data/ Command control pin. When the pin is pulled high, the data at D
7
-D
0
is treated as display data.
When the pin is pulled low, the data at D
7
-D
0
will be transferred to the command register.
7.2 R/
W
(
WR
)
This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used
as R/W signal input. Read mode will be carried out when this pin is pulled high and write mode when low.
When interfacing to a 8080-microprocessor, this pin will be the
WR
input. Data write operation is initiated when
this pin is pulled low and the chip is selected.
This pin must be fixed to high or low in serial mode.
7.3 DVDD & AVDD
Digital and Analog Power supply pin.
7.4 DVSS & AVSS
Ground.
7.5 E(
RD
)
This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used
as the enable signal, E. Read/ Write operation is initiated when this pin is pulled high and the chip is selected.
When interfacing to a 8080-microprocessor, this pin receives the
RD
signal. Data read operation is initiated when
this pin is pulled low and the chip is selected.
This pin must be fixed to high or low in serial mode.
7.6
CS
This pin is the chip select input.
7.7 D
7
-D
0
These pins are the 8-bit bi-directional data bus to be connected to the microprocessor in parallel interface mode.
In 8-bit bus mode, D
7
is the MSB while D
0
is the LSB. In 4-bit bus mode, it is needed to transfer 4-bit data (through
D
7
-D
4
) by two times. The high order bits (for 8-bit mode D
7
-D
4
) are written before the low order bits (for 8-bit mode
D
3
-D
0
) in write transaction and low order bits (8-bit mode D
3
-D
0
) are read before the high order bits (8-bit mode D
7
-
D
4
) in read transaction. The D
3
-D
0
pins must be fixed to high or low in 4-bit bus mode. After resets, SSD1800
considers first 4-bit data from MPU as the high order bits.
When serial mode is selected, D
7
is the serial data input (SDA) and D
6
is the serial clock input (SCK). D5-D0 must
be fixed to high or low in serial mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSD1800AV | LCD Segment / Common Driver with Controller |
| SSD1800Z | LCD Segment / Common Driver with Controller |
| SSD1801 | LCD Segment / Common Driver with Controller for Character Display System |
| SSD1801AV | LCD Segment / Common Driver with Controller for Character Display System |
| SSD1801Z | LCD Segment / Common Driver with Controller for Character Display System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSD1800AV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1800Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1801 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller for Character Display System |
| SSD1801AV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller for Character Display System |
| SSD1801Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Segment / Common Driver with Controller for Character Display System |
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