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參數(shù)資料
| 型號： | SSD1702Z |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 240-outputs LCD driver |
| 中文描述： | 240 - LCD驅(qū)動輸出 |
| 文件頁數(shù)： | 20/47頁 |
| 文件大?。?/td> | 586K |
| 代理商： | SSD1702Z |
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Solomon Systech
Dec 2003
P 20/46 Rev 1.1
SSD1702
Pin Name
SEGMENT MODE
COMMON MODE
L/R
L/R selects the scan direction of display
data output.
When L/R is set to L, data is read
sequentially at the direction of Y240 to Y1.
When L/R is set to H, data is read
sequentially at the direction of Y1 to Y240.
Refer to Table 8 and Table 9 for more
illustration.
L/R selects shift direction of shift register.
When L/R is set to L, data is shifted from
Y240 to Y1.
When L/R is set to H, data is shifted from
Y1 to Y240.
Refer to Table 10 for more illustration.
DISPOFF#
This is the display off control pin.
When DISPOFF# is set to H, the input
signal is level-shifted from logic voltage
level to LCD driving voltage level and
controls LCD drive circuit.
When it is set to L, the contents stored in
the line latch will be reset and Y1-Y240 will
output V
5
level. However, data can still be
read into data latch regardless of the
condition of DISPOFF#.
After the DISPOFF# function is cancelled,
the driver will output deselected level (V
12
or V
43
, depends on the level of FR) until it
encounters a falling edge of LP.
DISPOFF# removal time must meet the
AC characteristics shown in Table 14 and
Table 15. Otherwise, the driver may not
be able to output the correct data.
This is the display off control pin.
When DISPOFF# is set to H, the input
signal is level-shifted from logic voltage
level to LCD driving voltage level and
controls the LCD driving circuit.
When it is set to L, the contents stored in
the shift register will be reset and Y1-Y240
will output V
5
.
After the DISPOFF# function is cancelled,
the driver will output deselected level (V
12
or V
43
, depends on the level of FR) until it
encounters a falling edge of LP.
DISPOFF# removal time must meet the
AC characteristics shown in Table 16.
Otherwise, the driver may not be able to
output the correct data.
D0 – D7
These are display data input pins.
For 4 bits operation, only D0 - D3 are used
and D4 - D7 should be connected to either
VDD or VSS.
D0 - D6 are not used in common mode.
They should be tied to VSS.
D7 is used as input pin in dual mode. Data
is input starting from the 121
st
bit
according to the data shift register.
XCK
This is the shift clock input pin. Data is
read at the falling edge of the clock pulse.
It is not used in common mode. It should
be connected to VSS or left open.
LP
This is the latch pulse input pin. Data is
latched at the falling edge of the clock
pulse.
This is the bi-directional shift register clock
pulse input pin. Data is shifted at the falling
edge of this clock pulse.
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