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參數(shù)資料
| 型號(hào)： | SSD1339Z |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 132RGB × 132 2智能圖標(biāo)行點(diǎn)陣的OLED /短差段/驅(qū)動(dòng)器與控制器通用 |
| 文件頁數(shù)： | 22/59頁 |
| 文件大?。?/td> | 916K |
| 代理商： | SSD1339Z |
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Solomon Systech
Jul 2005
P 22/59 Rev 1.1
SSD1339
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
132 x 133 x 18bits.
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display.
Each pixel has 18-bit data. Each sub-pixels for color A, B and C have 6 bits. The arrangement of data
pixel in graphic display data RAM is shown below.
Figure 8 – Graphic Display Data RAM Structure
Data access in 262k colors mode
In 262k colors depth mode, there are different MCU interface communication modes to access graphic
display data RAM in OLED driver.
For 18 bits mode, the communication is made up of one session of 18 data bits. MCU transmits all bits to
write
one
18-bit pixel data into OLED driver. This 18-bit mode can be selected by setting the A[3] bit in
command A0 to 1.
17
16
15
14
13
12
11
10
Data bits
C
5
C
4
C
3
C
2
C
1
C
0
B
5
B
4
Bit
9
B
3
8
B
2
7
B
1
6
B
0
5
A
5
4
A
4
3
A
3
2
A
2
1
A
1
0
A
0
Figure 9 – 262k color depth data writing sequence in 18-bit MCU interface
For the 1
st
option of the two 16-bit modes, the communication is divided into two sessions of 16 data bits.
MCU transmits two 16-bit words to write
one
18-bit pixel data into OLED driver. Mode 1 is selected by
setting A0h register A[7:6] bits to 10b. In below, A1, B1, C1 are pixel bits for color A, B and C, and “X”
stands for don’t care value.
Normal
Remap
Data
Format
:
:
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
C4
C3
C2
C1
C0
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
C4
C3
C2
C1
C0
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
C4
C3
C2
C1
C0
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
C4
C3
C2
C1
C0
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
C4
C3
C2
C1
C0
A4
A3
A2
A1
A0
B5
B4
B3
B2
B1
B0
C4
C3
C2
C1
C0
COM
Normal
0
1
2
Remap
132
131
130
OUTPUT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
COM0
COM1
COM2
:
:
:
130
131
132
2
1
0
COM130
COM131
COM132
SA0
SB0
SC0
SA1
SB1
SC1 SA2 SB2 SC2
:
SA129
SB129
SC129
SA130
SB130
SC130
SA131
SB131
SC131
:
:
Row
Address
2
129
129
2
0
131
:
Column
Address
SEG OUTPUT
1
131
0
130
1
130
no. of bits of data in this cell
A5
C5
A5
C5
C5
C5
C5
C5
A5
A5
A5
A5
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