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| 型號： | SSD1339Z |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 132RGB × 132 2智能圖標(biāo)行點陣的OLED /短差段/驅(qū)動器與控制器通用 |
| 文件頁數(shù)： | 19/59頁 |
| 文件大小： | 916K |
| 代理商： | SSD1339Z |
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SSD1339
Rev 1.1
P 19/59 Jul 2005
Solomon Systech
7. FUNCTIONAL BLOCK DISCRIPTIONS
Oscillator Circuit and Display Time Generator
Divider
Internal
Oscillator
Fosc
M
U
X
CL
CLK
DCLK
Display
Clock
CLS
Figure 5 – Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry. The operation clock (CLK) can be generated
either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is
pulled high, internal oscillator is chosen. Pulling CLS pin low disables internal oscillator and external
clock must be connected to CL pins for proper operation. When the internal oscillator is selected, its
output frequency Fosc can be changed by command B3h.
In some COF packages of SSD1339, CLS pin is tied to high internally and the internal oscillator is
selected in these packages.
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor can
be programmed from 1 to 16 by command B3h.
Reset Circuit
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 132x132 Display Mode
3. Normal segment and display data column address and row address mapping (SEG0 mapped to
address 00H and COM0 mapped to address 00H)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 80H
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