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參數(shù)資料
| 型號： | SSD1303T8R1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 132 × 64點陣的OLED /短差段/驅動器與控制器通用 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大小： | 586K |
| 代理商： | SSD1303T8R1 |
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Solomon Systech
May 2005
P 16/56 Rev 1.7
SSD1303
7.4 MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/W (WR#), E (RD#), D/C, CS#. When
the R/W (WR#) pin is pulled HIGH, Read operation from the Graphic Display Data RAM (GDDRAM) or the
status register occurs. When the R/W (WR#) pin is pulled LOW, Write operation to Display Data RAM or
Internal Command Registers occurs, depending on the status of D/C input. The E (RD#) input serves as
data latch signal (clock) when HIGH provided that CS# is LOW. Refer to Parallel Interface Timing Diagram
of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed, which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 5 below.
Figure 5 - Display data read back procedure - insertion of dummy read
7.5 MPU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/W (WR#), E (RD#), D/C, CS#. The E
(RD#) input serves as data read latch signal (clock) when it is LOW provided that CS# is LOW. Display data
or status register read is controlled by D/C signal.
R/W (WR#) input serves as data write latch signal (clock) when it is HIGH and provided that CS# is LOW.
Display data or command register write is controlled by D/C. Refer to Parallel Interface Timing Diagram of
8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first
actual display data read.
n+2
n+1
Write column
address
Dummy read
Data read1
R/W#
(W/R#)
Data bus
N
n
E (RD#)
Data read2
Data read3
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| SSD1303Z | 132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| SSD1332 | OLED/PLED Segment/Common Driver with Controller |
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| SSD1339 | 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SSD1303T9R1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| SSD1303Z | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| SSD1332 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OLED/PLED Segment/Common Driver with Controller |
| SSD1332U1R1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OLED/PLED Segment/Common Driver with Controller |
| SSD1339 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
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