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參數(shù)資料
| 型號： | SPT7861SCU |
| 廠商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC28 |
| 封裝： | DIE-28 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 91K |
| 代理商： | SPT7861SCU |
SPT
5
2/10/98
SPT7861
Figure 2 - Typical Interface Circuit
Since only 16 comparators are used, a huge power savings
is realized.
The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparator's
response to a reference zero.
The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration voltage for
each ADC section.
Capacitive displacement currents, which can induce sam-
pling error, are minimized since only one comparator
samples the input during a clock cycle.
The total input capacitance is very low since sections of the
converter which are not sampling the signal are isolated
from the input by transmission gates.
VOLTAGE REFERENCE
The SPT7861 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. The lower side of the
ladder is typically tied to AGND (0.0 V), but can be run up to
2.0 V with a second reference. The analog input voltage
range will track the total voltage difference measured be-
tween the ladder sense lines, VRHS and VRLS.
VRHF
VRLS
VRLF
VRHS
VIN
CLK
VCAL
DAV
D10
D0
EN
AVDD
AGND
DGND* DVDD
Ref In
(+4 V)
VIN
CLK IN
Enable/Tri-State
(Enable = Active Low)
Interfacing
Logics
+D5
SPT7861
DGND
+
10 F
+5 V
Digital
+5 V
Digital
RTN
+D5
FB3
NOTES: 1) FB3 is to be located as closely to the device as possible.
2) There should be no additional connections to the right of FB1 and FB2.
3) All capacitors are 0.1 F surface-mount unless otherwise specified.
4) FB1, FB2 and FB3 are 10 H inductors or ferrite beads.
FB1
FB2
+A5
AGND
+
10 F
+5 V
Analog
+5 V
Analog
RTN
+A5
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
Figure 3 - Ladder Force/Sense Circuit
AGND
VRHF
VRHS
VRLS
VRLF
VIN
1
2
3
5
6
7
+
-
+
-
All capacitors are 0.01 F
4
N/C
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations. By
using the configuration shown in figure 3, offset and gain
errors of less than
±2 LSB can be obtained.
Figure 4 - Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
R/2
R
R/2
R=30
(typ)
All capacitors are 0.01 F
VRLF (AGND)
0.0 V
VRLS
(0.075 V)
VRHS
(+3.91 V)
90 mV
75 mV
+4.0 V
External
Reference
In cases in which wider variations in offset and gain can be
tolerated, VRef can be tied directly to VRHF and AGND can be
tied directly to VRLF as shown in figure 4. Decouple force and
sense lines to AGND with a .01
F capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The reference ladder circuit shown in figure 4 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from VRHF to VRHS is not equivalent
to the voltage drop from VRLF to VRLS.
Typically, the top side voltage drop for VRHF to VRHS will equal:
VRHF - VRHS = 2.25 % of (VRHF - VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will equal:
VRLS - VRLF = 1.9 % of (VRHF - VRLF) (typical).
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