參數(shù)資料
型號: SPI-4
廠商: Electronic Theatre Controls, Inc.
英文描述: Core w/ FIFOs V1.0 For Altera PLDs
中文描述: 核心瓦特/先進(jìn)先出為Altera可編程邏輯器件1.0
文件頁數(shù): 1/3頁
文件大?。?/td> 95K
代理商: SPI-4
Product Brief
SPI-4 Phase 1
Core w/ FIFOs V1.0
For Altera PLDs
June 2001
Features
odel
are
Standards to Silicon
OIF-compliant
(compatible with AMCC FlexBUS-4)
with FIFOs
SPI-4
Phase
1
ATM, Packet Over SONET (POS),
and Direct Data Mapping
1
modes
Single- and multi-link operation,
scalable from 1 to 16 links.
Programmable per-port bandwidth
allocation
Programmable
programmable almost empty/almost
full thresholds.
FIFO
size
with
Programmable burst size
Automatic link selection in the
Source block based on Source
FIFO threshold and flow control
information.
64-bit data bus width.
Parity
data and control words
generation/checking
over
Altera’s Atlantic Interface on user’s
side.
Full synchronous design, exceeds:
Clk = 200 MHz
Fully automatic test bench including
driver/monitor.
Easy to use in Mux/Demux and
bridge functions
Standards Compliance
OIF SPI-4 Phase 1
AMCC FlexBUS-4
1
Direct Data Mapping is a raw data mode
supported in AMCC’s Ganges device.
Benefits
Faster FPGA and ASIC development for
improved time-to-market with FlexBUS-
4 functions
Lower development cost through design
reuse
Available source code licensing for easy
design integration and migration to gate
arrays or ASICs
Ample design flexibility using control
signals and generics/parameters
Verified functionality and standards
compliance
Description
The Optical Interworking Forum’s (OIF) SPI-
4 Phase 1 interface allows the
interconnection of Physical Layer devices to
Link Layer devices in 10Gb/s ATM, POS,
and Ethernet applications. Modelware’s
SPI-4 Phase 1 core performs the interface
functions on both sides of the interface as
shown in Figure 1and Figure 2.
Spi4
Link
Layer
Control
Status
SPI-4
I/F
PluriBus
Interface
Tx
FIFO(s)
Rx
FIFO(s)
PHY
Layer
Processor
Line Tx
Data
Line Rx
Data
Spi4Tx
Spi4Rx
Figure 1: SPI-4 Phase 1 PHY Layer Application
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