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Semiconductor Group
7
SPH 4692
Pin 18
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 18 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time
t
UL
after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per page 133 is represented on page 135 for a line
voltage barely above the lower acceptable limit time
t
0
the following voltages built up:
–
V
16
corresponding to the half-wave charge current over
R
1
–
V
2
to
V
2 max
(typically 6.6 V)
–
V
3
to the value determined by the divider
R
10
/
R
11
.
The current drawn by the IC in this case is less than 0.8 mA.
If
V
16
reaches the threshold
V
16 E
(time point
t
1
), the IC switches on the internal reference voltage.
The current draw max. rises to 12 mA. The primary current-voltage reproducer regulates
V
2
down
to
V
2B
and the starting impulse generator generates the starting impulses from time point
t
5
to
t
6
.
The feedback to pin 18 starts the next impulse and so on. All impulses including the starting impulse
are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-
circuit event, i.e.
V
1
= 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of
V
2
decrease rapidly, as the starting
attempt is aborted (pin 15 is switched to low). As the IC remains switched on,
V
16
further decreases
to
V
16
. The IC switches off;
V
16
can rise again (time point
t
4
) and a new start-up attempt begins at
time point
t
1
. If the rectified alternating line voltage (primary voltage) collapses during load,
V
3
can
fall below
V
3 A
, as is happening at time point
t
3
(switch-on attempt when voltage is too low). The
primary voltage monitor then clamps
V
3
to
V
3 S
until the IC switches off (
V
16
<
V
16 A
). Then a new
start-up attempt begins at time point
t
1
.