參數(shù)資料
型號： SN74GTLP21395GQNR
廠商： Texas Instruments, Inc.
英文描述： TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
中文描述： 兩個1位LVTTL至GTLP可調EDGE的速率總線收發(fā)器與劈開LVTTL港口，反饋路徑，和可選的極性
文件頁數(shù)： 3/21頁
文件大?。?/td> 439K
代理商： SN74GTLP21395GQNR
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C
–
JUNE 2001
–
REVISED NOVEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC
–
DW
Tube
SN74GTLP21395DW
GTLP21395
Tape and reel
SN74GTLP21395DWR
–
40
°
C to 85
°
C
TSSOP
–
PW
Tape and reel
SN74GTLP21395PWR
GU395
TVSOP
–
DGV
Tape and reel
SN74GTLP21395DGVR
GU395
VFBGA
–
GQN
Tape and reel
SN74GTLP21395GQNR
GU395
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY,
and 2T/C control 2A, 2B, and 2Y.
OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high,
the B-port output is disabled.
A separate LVTTL A input and Y output provide a feedback path for control and diagnostics monitoring. OEBY
controls the Y output. When OEBY is low, the Y output is active. When OEBY is high, the Y output is disabled.
T/C selects polarity of data transmission in both directions. When T/C is high, data transmission is true, and
A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary,
and inverted A data goes to the B bus and inverted B data goes to the Y bus.
Function Tables
OUTPUT CONTROL
INPUTS
OUTPUT
MODE
T/C
OEAB
OEBY
X
H
H
Z
Isolation
H
L
H
A data to B bus
True transparent
H
H
L
B data to Y bus
H
L
L
A data to B bus, B data to Y bus
True transparent
with feedback path
L
L
H
Inverted A data to B bus
Inverted transparent
L
H
L
Inverted B data to Y bus
L
L
L
Inverted A data to B bus,
Inverted B data to Y bus
Inverted transparent
with feedback path
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT
ERC
LOGIC LEVEL
OUTPUT
B-PORT
EDGE RATE
H
Slow
L
Fast
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相關代理商/技術參數(shù)
參數(shù)描述
SN74GTLP21395PW 功能描述:特定功能邏輯 2 1-Bit LVTTL/GTLP Bus Xcvr Adj-Eg-Rate RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74GTLP21395PWE4 功能描述:總線收發(fā)器 Quad Bus Buff Gate W/3-St Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74GTLP21395PWG4 功能描述:特定功能邏輯 Two 1B LVTTL GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74GTLP21395PWR 功能描述:轉換 - 電壓電平 Dual 1bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8
SN74GTLP22033DGGR 功能描述:轉換 - 電壓電平 8bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8
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