參數(shù)資料
型號(hào): SN74ALVCH16245DGV
廠商: Texas Instruments, Inc.
英文描述: 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
中文描述: 16位總線收發(fā)器和三態(tài)輸出
文件頁數(shù): 1/8頁
文件大?。?/td> 131K
代理商: SN74ALVCH16245DGV
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ALVCH16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES015F – JULY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This
transceiver is designed for 1.65-V to 3.6-V V
CC
operation.
16-bit
(dual-octal)
noninverting
bus
The
asynchronous communication between data
buses. The control-function implementation
minimizes external timing requirements.
SN74ALVCH16245
is
designed
for
This device can be used as two 8-bit transceivers
or one 16-bit transceiver. It allows data
transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16245 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1999, Texas Instruments Incorporated
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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