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參數(shù)資料
| 型號： | SN74ALVC3651PCB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 2048】36 SYNCHRONOU仛先入先出存儲器 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 383K |
| 代理商： | SN74ALVC3651PCB |
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SN74ALVC3651
2048
×
36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDMS025A – OCTOBER 1999 – REVISED DECEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
W/RA
I
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for
a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
W/RB
I
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for
a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is low.
detailed description
reset
The SN74ALVC3651 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset
initializes the memory-read and-write pointers and forces the IR flag low, the OR flag high, the AE flag low, and
the AF flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset,
IR is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power up
before data is written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN74ALVC3651 are used to hold the offset values for the AE and AF flags. The AE flag
offset register is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded with
a value in three ways: one of two preset values is loaded into the offset registers, parallel load from port A, or
serial load. The offset-register-programming mode is chosen by the flag select (FS1, FS0) inputs during a
low-to-high transition on RST (see Table 1).
Table 1. Flag Programming
FS1
FS0
RST
↑
↑
↑
↑
X AND Y REGISTERS
H
H
Serial load
H
L
64
L
H
8
L
L
Parallel load from port A
X register holds the offset for AE; Y register holds the
offset for AF.
preset values
If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of an RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high
transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA.
The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.
Each offset register of the SN74ALVC3651 uses port-A inputs (A10–A0). The highest number input is used as
the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to
2044. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.
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參數(shù)描述 |
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| SN74ALVC7803-20DL | 功能描述:先進(jìn)先出 3.3V ABT 16-Bit Buff/Drv W/3-St Otpt RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-20DLR | 功能描述:先進(jìn)先出 512 x 18 3.3-V Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-25DL | 功能描述:先進(jìn)先出 16-Bit Buffer/Driver With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-25DLR | 功能描述:先進(jìn)先出 512 x 18 3.3-V Synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-40DL | 功能描述:先進(jìn)先出 16-Bit Bus Trnscvr With 3-State Outputs RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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