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| 型號： | SN74ALVC16721DGG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP-56 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 131K |
| 代理商： | SN74ALVC16721DGG |
SN74ALVC16721
3.3V 20BIT FLIPFLOP
WITH 3STATE OUTPUTS
SCAS267A MARCH 1993 REVISED MAY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D Member of the Texas Instruments
Widebus
Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Bus Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 20-bit flip-flop is designed specifically for
low-voltage (3.3-V) VCC operation; it is tested at
2.5-V, 2.7-V, and 3.3-V VCC.
The SN74ALVC16721’s 20 flip-flops are edge-
triggered D-type flip-flops with qualified clock
storage. On the positive transition of the clock
(CLK) input, the device provides true data at the
Q outputs if the clock-enable (CLKEN) input is low.
If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the
20 outputs in either a normal logic state (high
or low level) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive
bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74ALVC16721 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16721 is characterized for operation from 40
°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
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OE
Q1
Q2
GND
Q3
Q4
VCC
Q5
Q6
Q7
GND
Q8
Q9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
VCC
Q17
Q18
GND
Q19
Q20
NC
CLK
D1
D2
GND
D3
D4
VCC
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
D18
GND
D19
D20
CLKEN
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1995, Texas Instruments Incorporated
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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| SN74AS1008ADE4 | AS SERIES, QUAD 2-INPUT AND GATE, PDSO14 |
| SN74AS286DRE4 | AS SERIES, 9-BIT PARITY GENERATOR/CHECKER, TRUE OUTPUT, PDSO14 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVC16721DL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74ALVC16820DL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74ALVC16834DGGR | 功能描述:通用總線函數(shù) 16bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DGVR | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVC16834DL | 功能描述:通用總線函數(shù) 18bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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