參數(shù)資料
型號(hào)： SN74ACT3651PQ
廠商： Texas Instruments, Inc.
英文描述： Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
中文描述： 2048】36時(shí)鐘先入先出存儲(chǔ)器
文件頁(yè)數(shù)： 22/26頁(yè)
文件大?。?/td> 376K
代理商： SN74ACT3651PQ
SN74ACT3651
2048
×
36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS439D – JUNE 1994 – REVISED FEBRUARY 1999
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
’ACT3651-15
MIN
’ACT3651-20
MIN
’ACT3651-30
MIN
UNIT
MAX
MAX
MAX
fclock
tc
tw(CH)
tw(CL)
tsu(D)
Clock frequency, CLKA or CLKB
66.7
50
33.4
MHz
Clock cycle time, CLKA or CLKB
15
20
30
ns
Pulse duration, CLKA and CLKB high
6
8
12
ns
Pulse duration, CLKA and CLKB low
Setup time, A0–A35 before CLKA
↑
and B0–B35 before CLKB
↑
Setup time, CSA, W/RA, ENA, and MBA before CLKA
↑
;
CSB, W/RB, ENB, MBB, RTM, and RFM before CLKB
↑
Setup time, RST low before CLKA
↑
or CLKB
↑
Setup time, FS0 and FS1 before RST high
Setup time, FS0/SD before CLKA
↑
Setup time, FS1/SEN before CLKA
↑
Hold time, A0–A35 after CLKA
↑
and B0–B35 after CLKB
↑
Hold time, CSA, W/RA, ENA, and MBA after CLKA
↑
;
CSB, W/RB, ENB, RFM, and MBB after CLKB
↑
Hold time, RST low after CLKA
↑
or CLKB
↑
Hold time, FS0 and FS1 after RST high
6
8
12
ns
4
5
6
ns
tsu(EN)
4
5
6
ns
tsu(RS)
tsu(FS)
tsu(SD)
tsu(SEN)
th(D)
5
6
7
ns
12
13
14
ns
4
5
6
ns
5
6
7
ns
1
1
1
ns
th(EN)
0
0
0
ns
th(RS)
th(FS)
th(SP)
th(SD)
th(SEN)
tsk(1)§
tsk(2)§
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Applies only when serial load method is used to program flag offset registers
§Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
5
6
7
ns
2
3
3
ns
Hold time, FS1/SEN high after RST high
Hold time, FS0/SD after CLKA
↑
Hold time, FS1/SEN after CLKA
↑
Skew time between CLKA
↑
and CLKB
↑
for OR and IR
Skew time between CLKA
↑
and CLKB
↑
for AE and AF
1
1
1
ns
0
0
0
ns
0
0
0
ns
6
8
10
ns
12
16
20
ns
相關(guān)PDF資料
PDF描述
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參數(shù)描述
SN74ACT373DB 制造商:Rochester Electronics LLC 功能描述:- Bulk
SN74ACT373DBR 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74ACT373DBRE4 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74ACT373DBRG4 功能描述:閉鎖 Octal D-Type Transp RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
SN74ACT373DW 功能描述:閉鎖 Tri-St Octal D-Type RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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