參數(shù)資料
型號(hào)： SN74ACT3641PCB
廠商： Texas Instruments, Inc.
英文描述： Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
中文描述： 1024】36時(shí)鐘先入先出存儲(chǔ)器
文件頁(yè)數(shù)： 8/26頁(yè)
文件大?。?/td> 379K
代理商： SN74ACT3641PCB
SN74ACT3641
1024
×
36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO write/read operation (continued)
Table 3. Port-B Enable Function Table
CSB
W/RB
ENB
MBB
CLKB
B0–B35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
L
L
X
X
↑
↑
X
↑
X
↑
In high-impedance state
None
L
L
H
L
In high-impedance state
None
L
L
H
H
In high-impedance state
Mail2 write
L
H
L
L
Active, FIFO output register
None
L
H
H
L
Active, FIFO output register
FIFO read
L
H
L
H
Active, mail1 register
None
L
H
H
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When the OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high
transition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register only
when a FIFO read is selected by CSB, W/RB, ENB, and MBB.
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the
flag’s reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of words stored in memory.
Table 4. FIFO Flag Operation
NUMBER OF WORDS IN
FIFO
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
OR
AE
AF
IR
0
L
L
H
H
1 to X
H
L
H
H
(X + 1) to [1024 – (Y + 1)]
H
H
H
H
(1024 – Y) to 1023
H
H
L
H
1024
H
H
L
L
X is the almost-empty offset for AE. Y is the almost-full offset for AF.
When a word is present in the FIFO output register, its previous memory
location is free.
相關(guān)PDF資料
PDF描述
SN74ACT3641PQ Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs, Pb-free; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN74ACT3651PCB Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75
SN74ACT3651PQ Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
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