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參數(shù)資料
| 型號： | SN74ABT8652DW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 8-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 506K |
| 代理商： | SN74ABT8652DW |
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SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→ BIT 0
MSB
→ LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/16-bit mode (PRPG)
X10
Parallel-signature analysis/16-bit mode (PSA)
011
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)
In general, while the control input BSCs (bits 37–32) are not included in the sample, toggle, PSA, PRPG, or
COUNT algorithms, the output-enable BSCs (bits 37–36 of the BSR) do control the drive state (active or high
impedance) of the selected device output terminals. These BCR instructions are valid only when the device is
operating in one direction of data flow (that is, OEAB
= OEBA). Otherwise, the bypass instruction is operated.
PSA input masking
Bits 10–3 of the BCR specify device input terminals to be masked from PSA operations. Bit 10 selects masking
for device input pin A8 during A-to-B data flow or for device input pin B8 during B-to-A data flow. Bit 3 selects
masking for device input terminals A1 or B1 during A-to-B or B-to-A data flow, respectively. Bits intermediate
to 10 and 3 mask corresponding device input terminals in order, from most significant to least significant, as
indicated in Table 3. When the mask bit that corresponds to a particular device input has a logic 1 value, the
device input pin is masked from any PSA operation, i.e., the state of the device input pin is ignored and has no
effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device
input is not masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input terminals is captured in the shift-register elements of the selected
BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and
applied to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs
is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device
output terminals on each falling edge of TCK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT8652DWE4 | 功能描述:特定功能邏輯 Device w/Octal Bus Trnscvr & Register RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT8652DWG4 | 功能描述:特定功能邏輯 Scan Test Devices RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT8652DWR | 功能描述:總線收發(fā)器 Device w/Octal Bus Trnscvr & Register RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ABT8652DWRE4 | 功能描述:特定功能邏輯 Device w/Octal Bus Trnscvr & Register RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT8652DWRG4 | 功能描述:特定功能邏輯 Scan Test Devices RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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