參數(shù)資料
型號(hào): SN74ABT162601DGG
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
中文描述: 18位通用總線收發(fā)3態(tài)輸出
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 124K
代理商: SN74ABT162601DGG
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
B-Port Outputs Have Equivalent 25-
Series Resistors, So No External Resistors
Are Required
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25
°
C
High-Impedance State During Power Up
and Power Down
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low,
the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A
is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-
series resistors
to reduce overshoot and undershoot.
When V
CC
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus, EPIC-
ΙΙ
B, and UBT are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT162601 . . . WD PACKAGE
SN74ABT162601 . . . DGG OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
CLKENBA
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