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    • 參數(shù)資料
      型號: SN54LVCH245AFK
      廠商: Texas Instruments, Inc.
      英文描述: OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
      中文描述: 八路總線收發(fā)器與三態(tài)輸出
      文件頁數(shù): 1/9頁
      文件大小: 127K
      代理商: SN54LVCH245AFK
      SN54LVCH245A, SN74LVCH245A
      OCTAL BUS TRANSCEIVERS
      WITH 3-STATE OUTPUTS
      SCES008F – JULY 1995 - REVISED JUNE 1998
      1
      POST OFFICE BOX 655303
      DALLAS, TEXAS 75265
      EPIC
      (Enhanced-Performance Implanted
      CMOS) Submicron Process
      Typical V
      OLP
      (Output Ground Bounce)
      < 0.8 V at V
      CC
      = 3.3 V, T
      A
      = 25
      °
      C
      Typical V
      OHV
      (Output V
      OH
      Undershoot)
      > 2 V at V
      CC
      = 3.3 V, T
      A
      = 25
      °
      C
      Power Off Disables Outputs, Permitting
      Live Insertion
      ESD Protection Exceeds 2000 V Per
      MIL-STD-883, Method 3015; Exceeds 200 V
      Using Machine Model (C = 200 pF, R = 0)
      Latch-Up Performance Exceeds 250 mA Per
      JESD 17
      Support Mixed-Mode Signal Operation on
      All Ports (5-V Input/Output Voltage With
      3.3-V V
      CC
      )
      Bus Hold on Data Inputs Eliminates the
      Need for External Pullup/Pulldown
      Resistors
      Package Options Include Plastic
      Small-Outline (DW), Shrink Small-Outline
      (DB), and Thin Shrink Small-Outline (PW)
      Packages, Ceramic Flat (W) Package,
      Ceramic Chip Carriers (FK), and DIPs (J)
      description
      The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V V
      CC
      operation and the
      SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V V
      CC
      operation.
      These devices are designed for asynchronous communication between data buses. These devices transmit
      data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
      direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
      effectively isolated.
      Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
      in a mixed 3.3-V/5-V system environment.
      To ensure the high-impedance state during power up or power down, OE should be tied to V
      CC
      through a pullup
      resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
      Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
      The SN54LVCH245A is characterized for operation over the full military temperature range of –55
      °
      C to 125
      °
      C.
      The SN74LVCH245A is characterized for operation from –40
      °
      C to 85
      °
      C.
      Copyright
      1998, Texas Instruments Incorporated
      On products compliant to MIL-PRF-38535, all parameters are tested
      unless otherwise noted. On all other products, production
      processing does not necessarily include testing of all parameters.
      PRODUCTION DATA information is current as of publication date.
      Products conform to specifications per the terms of Texas Instruments
      standard warranty. Production processing does not necessarily include
      testing of all parameters.
      EPIC is a trademark of Texas Instruments Incorporated.
      Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
      Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
      SN54LVCH245A . . . J OR W PACKAGE
      SN74LVCH245A . . . DB, DW, OR PW PACKAGE
      (TOP VIEW)
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      5
      6
      7
      8
      9
      10
      20
      19
      18
      17
      16
      15
      14
      13
      12
      11
      DIR
      A1
      A2
      A3
      A4
      A5
      A6
      A7
      A8
      GND
      V
      CC
      OE
      B1
      B2
      B3
      B4
      B5
      B6
      B7
      B8
      SN54LVCH245A . . . FK PACKAGE
      (TOP VIEW)
      3
      2
      1 20 19
      9 10 11 12 13
      4
      5
      6
      7
      8
      18
      17
      16
      15
      14
      B1
      B2
      B3
      B4
      B5
      A3
      A4
      A5
      A6
      A7
      A
      A
      D
      B
      B
      O
      A
      G
      B
      V
      C
      相關(guān)PDF資料
      PDF描述
      SN54LVCH245AJ Analog Multiplexers/Demultiplexers; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50
      SN54LVCH245AW Analog Multiplexers/Demultiplexers; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500
      SN74LVCH245ADB OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
      SN54LVT162240 Analog Multiplexers/Demultiplexers; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500
      SN54LVT162244A Analog Multiplexers/Demultiplexers; Package: SOIC 16 LEAD; No of Pins: 16; Container: Rail; Qty per Container: 48
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
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