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參數(shù)資料
| 型號： | SN54LS160J |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS |
| 中文描述： | BCD碼十年計數(shù)器/ 4位二進制計數(shù)器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 79K |
| 代理商： | SN54LS160J |
5-5
FAST AND LS TTL DATA
SN54/74LS160A
SN54/74LS161A
SN54/74LS162A
SN54/74LS163A
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
b l
Parameter
Limits
U i
Unit
Test Conditions
di i
Min
Typ
Max
tWCP
tW
ts
ts
th
th
trec
*CEP, CET or DATA
Clock Pulse Width Low
25
ns
VCC = 5.0 V
5 0 V
5 0 V
5 0 V
MR or SR Pulse Width
20
ns
Setup Time, other*
20
ns
Setup Time PE or SR
25
ns
Hold Time, data
3
ns
Hold Time, other
0
ns
Recovery Time MR to CP
15
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time re-
quired between the end of the reset pulse and the clock transi-
tion from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
CP
Q
tW(H)
tW(L)
trec
tPHL
tPHL
tPLH
OTHER CONDITIONS:
PE = MR (SR) = H
CEP = CET = H
OTHER CONDITIONS:
PE = L
P0 = P1 = P2 = P3 = H
tW
Q0
Q1
Q2
Q3
MR
CP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LS161J | BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS |
| SN54LS162J | BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS |
| SN74LS160D | Reference Design kit for ADNS-6000 |
| SN74LS160N | Reference Design kit for ADNS-5020 |
| SN74LS161D | Optical Mouse Sample Kit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54LS161AJ | 制造商:Texas Instruments 功能描述:Counter Single 4-Bit Sync Binary UP 16-Pin CDIP Tube 制造商:Texas Instruments 功能描述:COUNTER SGL 4BIT SYNC BINARY UP 16CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:4 BIT SYNC BINARY COUNTER |
| SN54LS162W | 制造商:Texas Instruments 功能描述: |
| SN54LS163AJ | 制造商:Texas Instruments 功能描述:Counter Single 4-Bit Sync Binary UP 16-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:SYNC 4-BIT BINARY COUNTER - Rail/Tube 制造商:Motorola Inc 功能描述:Counter, Up, 4 Bit Binary, 16 Pin, Ceramic, DIP |
| SN54LS164J | 制造商:Texas Instruments 功能描述:Shift Register Single 8-Bit Serial to Parallel 14-Pin CDIP Tube 制造商:Texas Instruments 功能描述:SHIFT REGISTER SGL 8BIT SERL TO PARALLEL 14CDIP - Rail/Tube |
| SN54LS165AJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:8-BIT PISO SHIFT REGISTER - Rail/Tube 制造商:Texas Instruments 功能描述:Shift Register Single 8-Bit Serial/Parallel to Serial 16-Pin CDIP Tube |
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