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參數(shù)資料
| 型號： | SN54HCT652W |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual EIA-423/EIA-232D Line Driver; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50 |
| 中文描述： | 八路總線收發(fā)器和寄存器具有三態(tài)輸出 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 152K |
| 代理商： | SN54HCT652W |
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179B – MARCH 1984 – REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
↑
↑
↑
H or L
↑
X
H or L
↑
H or L
↑
↑
↑
X
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
X
X
X
Input
Unspecified
Store A, hold B
H
H
X
Input
Output
Store A in both registers
L
X
X
X
X
Unspecified
Input
Hold A, store B
L
L
X
Output
Input
Store B in both registers
L
L
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
logic symbol
§
§This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the DW, JT, NT, and W packages.
OEBA
EN1 [BA]
21
3
23
G5
22
1
2
SBA
A1
4
B1
20
4D
EN2 [AB]
OEAB
CLKBA
CLKAB
SAB
G7
5
7
7
5
1
1
6D
≥
1
≥
1
1
2
C6
C4
A2
5
B2
19
A3
6
B3
18
A4
7
B4
17
A5
8
B5
16
A6
9
B6
15
A7
10
B7
14
A8
11
B8
13
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