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參數(shù)資料
| 型號： | SN54F109FK |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
| 中文描述： | 雙JK上升沿觸發(fā)器，沒有明確的和預置觸發(fā)器 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 73K |
| 代理商： | SN54F109FK |
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993
Copyright
1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and trying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
The SN54F109 is characterized for operation over
the full military temperature range of –55
°
C to
125
°
C. The SN74F109 is characterized for
operation from 0
°
C to 70
°
C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
H
L
L
X
↑
↑
↑
↑
L
X
X
H
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
Q0
H
Q0
L
H
H
H
H
H
H
X
X
Q0
Q0
The output levels are not guaranteed to meet the minimum
levels for VOH. Furthermore, this configuration s nonstable;
that is, it will not persist when PRE or CLR returns to its
inactive (high) level.
SN54F109 . . . J PACKAGE
SN74F109 . . . D OR N PACKAGE
(TOP VIEW)
SN54F109 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1
1
N
2
2
V
2
1
G
N
C
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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