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參數(shù)資料
| 型號(hào)： | SN54CDC586WD |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUPUTS |
| 中文描述： | 3.3 - V相位鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器具有三態(tài)OUPUTS |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | SN54CDC586WD |
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
output configuration A
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at one-half the CLKIN frequency, while outputs configured as 1x outputs
operate at the same frequency as CLKIN.
Table 1. Output Configuration A
INPUTS
OUTPUTS
SEL1
SEL0
1/2X
FREQUENCY
1X
FREQUENCY
L
L
None
All
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B
INPUTS
OUTPUTS
SEL1
SEL0
1X
FREQUENCY
2X
FREQUENCY
L
L
All
None
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3
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