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SN54AS181B, SN74AS181A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The SN54AS181B and SN74AS181A also can be used as comparators. The A = B output is internally decoded
from the function (F0, F1, F2, F3) outputs so that when two words of equal magnitude are applied at the A and
B inputs, the output assumes a high level to indicate equality (A = B). The ALU must be in the subtract mode
with C
n
= H when performing this comparison. The A = B output is open collector so that it can be wire-AND
connected to give a comparison for more than four bits. C
n + 4
also can be used to supply relative magnitude
information. The ALU must be placed in the subtract mode by placing the function-select inputs S3, S2, S1, and
S0 at L, H, H, and L, respectively.
INPUT
Cn
H
OUTPUT
Cn + 4
H
ACTIVE-LOW DATA
(Figure 1)
ACTIVE-HIGH DATA
(Figure 2)
A
≥
B
A < B
A
≤
B
A > B
H
L
L
H
A > B
A
≤
B
A < B
A
≥
B
L
L
These circuits not only incorporate all of the designer’s requirements for arithmetic operations, but also provide
16 possible functions of two Boolean variables without using external circuitry. These logic functions are
selected by the four function-select inputs with M at a high level to disable the internal carry. The 16 logic
functions are detailed in Tables 1 and 2 and include exclusive-OR, NAND, AND, NOR, and OR functions.
TYPICAL ADDITION TIME
(CL = 15 pF, RL = 280
, TA = 25
°
C)
PACKAGE COUNT
TIME USING
′
S181 AND
′
S182
ADDITION
NUMBER
OF BITS
ALUs
LOOK-AHEAD
CARRY
GENERATORS
CARRY METHOD
BETWEEN ALUs
1 to 4
11 ns
1
None
5 to 8
18 ns
2
Ripple
9 to 16
19 ns
3 or 4
1
Full look ahead
17 to 64
28 ns
5 to 16
2 to 5
Full look ahead
The SN54AS181B is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74AS181A is characterized for operation from 0
°
C to 70
°
C.
application note
An application-specific problem has been identified in the SN54AS181B device. The F0–F4 outputs exhibit
voltage transients when one or more B-data inputs transition from a high to a low state. The resultant voltage
transients can have an amplitude of 2 V relative to V
OL
with a width of 5 ns at an input threshold of 1.5 V. The
transient pulse occurs coincidentally with the high-to-low transition of the B-data input(s) and appears to be
caused by internal coupling.
In system operations in which this device is used, it is likely that transmission-line effects minimize this anomaly.
Narrow width of the voltage transient makes the pulse transparent to most circuitry; however, in certain
applications, the transients can cause system errors.