參數(shù)資料
型號(hào)： SN54ABT8952JT
廠商： Texas Instruments, Inc.
英文描述： SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
中文描述： 掃描測(cè)試設(shè)備與八進(jìn)制注冊(cè)總線收發(fā)器
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 365K
代理商： SN54ABT8952JT
SN54ABT8952, SN74ABT8952
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D – AUGUST 1992 – REVISED JULY 1996
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 4 and 5 illustrate the 16-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
=
A8-I
B8-O
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
Figure 4. 16-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
=
B8-I
A8-O
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
Figure 5. 16-Bit PRPG Configuration (OEAB=1, OEBA = 0)
相關(guān)PDF資料
PDF描述
SN54ABTE16245WD 16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
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SN54AC00J QUADRUPLE 2-INPUT POSITIVE-NAND GATES
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