參數(shù)資料
型號(hào): SN54ABT8652JT
廠商: Texas Instruments, Inc.
英文描述: SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS
中文描述: 掃描測(cè)試設(shè)備與八路總線收發(fā)器和寄存器
文件頁(yè)數(shù): 17/25頁(yè)
文件大?。?/td> 366K
代理商: SN54ABT8652JT
SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input terminals is compressed into an 8-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 8-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output
terminals on each falling edge of TCK. In addition, the shift-register elements of the opposite output BSCs count
carries out of the selected output BSCs extending the count to 16 bits. Figures 11 and 12 show the 8-bit
linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should
be scanned into the BSR before performing this operation.
=
=
M
A8-I
B8-O
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
MSB
LSB
Figure 11. 8-Bit PSA/COUNT Configuration (OEAB = 1, OEBA = 1)
=
=
M
B8-I
A8-O
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
MSB
LSB
Figure 12. 8-Bit PSA/COUNT Configuration (OEAB = 0, OEBA = 0)
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