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參數(shù)資料
| 型號(hào)： | SMJ626162 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 524288由16位2，銀行同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大小： | 647K |
| 代理商： | SMJ626162 |
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SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
burst sequence
All data for the ’626162 is written or read in a burst fashion—that is, a single starting address is entered into the
device and then the ’626162 internally accesses a sequence of locations based on that starting address. Some
of the subsequent accesses after the first access can be at preceding, as well as succeeding, column
addresses, depending on the starting address entered. This sequence can be programmed to follow either a
serial burst or an interleave burst (see Table 4, Table 5, and Table 6). The length of the burst can be programmed
to be either 1, 2, 4, 8, or full-page (256) accesses (see the section on setting the mode register). After a read
burst is completed (as determined by the programmed burst length), the outputs are in the high-impedance state
until the next read access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
0
2ND
1
START
0
2ND
1
Serial
1
0
1
0
Interleave
0
1
0
1
1
0
1
0
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1–A0
DECIMAL
2ND
1
BINARY
2ND
01
START
0
3RD
2
4TH
3
START
00
3RD
10
4TH
11
Serial
1
2
3
0
01
10
11
00
2
3
0
1
10
11
00
01
3
0
1
2
11
00
01
10
0
1
2
3
00
01
10
11
Interleave
1
0
3
2
01
00
11
10
2
3
0
1
10
11
00
01
3
2
1
0
11
10
01
00
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