參數(shù)資料
型號(hào)： SMJ626162
廠商： Texas Instruments, Inc.
英文描述： 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
中文描述： 524288由16位2，銀行同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁數(shù)： 15/42頁
文件大?。?/td> 647K
代理商： SMJ626162
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
’626162-12
MIN
’626162-15
MIN
’626162-20
MIN
UNIT
MAX
MAX
MAX
VOH
High-level output
voltage
IOH = –2 mA
2.4
2.4
2.4
V
VOL
Low-level output
voltage
IOL = 2 mA
0.4
0.4
0.4
V
II
Input current
(leakage)
0 V
≤
VI
≤
VCC,
All other pins = 0 V to VCC
±
10
±
10
±
10
μ
A
IO
Output current
(leakage)
0 V
≤
VO
≤
VCCQ, Output disabled
±
10
±
10
±
10
μ
A
ICC1
Average read or
write current
Burst length = 1,
tRC
≥
tRC MIN,
IOH/IOL= 0 mA
IOH/IOL = 0 mA,
One bank activated
(see Note 3)
Read latency = 2
85
75
70
mA
Read latency = 3
100
95
85
ICC2P
Precharge standby
current in
power-down mode
CKE
≤
VIL MAX,
CKE and CLK
tCK =
∞
(see Note 5)
tCK = MIN (see Note 4)
VIL MAX,
2
2
2
ICC2PS
2
2
2
mA
ICC2N
Precharge standby
current in
nonpower-down
mode
CKE
≥
VIH MIN,
tCK = MIN (see Note 4)
40
35
30
ICC2NS
CKE
≥
VIH MIN,
tCK =
∞
(see Note 5)
CLK
≤
VIL MAX,
2
2
2
mA
ICC3P
Active standby
current in
power-down mode
CKE
≤
VIL MAX,
One bank activated (see Note 4)
tCK = MIN
10
10
10
mA
ICC3PS
CKE and CLK
≤
VILMAX,
One bank activated (see Note 5)
tCK =
∞
10
10
10
ICC3N
Active standby
current in
nonpower-down
mode
CKE
≥
VIH MIN,
One bank activated (see Note 4)
tCK = MIN
55
45
40
mA
ICC3NS
CKE
≥
VIH MIN,
tCK =
∞
, One bank activated (see Note 5)
Continuous burst,
IOH/IOL = 0 mA,
All banks activated,
nCCD = one cycle
(see Note 6)
CLK
≤
VIL MAX,
15
15
15
ICC4
Burst current
Read latency = 2
165
130
110
mA
Read latency = 3
210
175
150
ICC5
Autorefresh
tRCMIN
tRC
≥
tRC MIN
Read latency = 2
120
100
80
mA
Read latency = 3
120
100
80
NOTES:
2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
3. Control and address inputs change state twice during tRC.
4. Control and address inputs change state once every 2
×
tCK.
5. Control and address inputs do not change state (stable).
6. Control and address inputs change state once every cycle.
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