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| 型號： | SMJ626162 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 524288由16位2，銀行同步動態(tài)隨機(jī)存取存儲器 |
| 文件頁數(shù)： | 11/42頁 |
| 文件大小： | 647K |
| 代理商： | SMJ626162 |
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SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupted bursts (continued)
CLK
DQ
READ Command
Interrupting
WRT Command
Q
D
D
DQMx
See Note B
nCCD = 5 Cycles
NOTES: A. For this example, assume read latency = 3 and burst length = 4.
B. DQMx must be high to mask output of the read burst on cycles (nCCD – 1), nCCD, and (nCDD + 1).
Figure 3. Read Burst Interrupted by Write Command
DQ
CLK
Q
Q
Interrupting
DEAC/DCAB
Command
READ Command
nHZP
nCCD = 2 Cycles
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
Data that was input on the previous cycle is written; no further data inputs are accepted (see Figure 5).
WRT, WRT-P
The new WRT (WRT-P) command and data inputs immediately supersede the write burst in progress
(see Figure 6).
DEAC, DCAB
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
mask the DQ bus such that the write recovery specification (tRWL) is not violated by the
interrupt (see Figure 7).
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