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| 型號： | SMJ55166 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 58/62頁 |
| 文件大?。?/td> | 1403K |
| 代理商： | SMJ55166 |
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SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057C – APRIL 1995 – REVISED JUNE 1997
58
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
ADDR
TRG
DSF
CASE I
SC
QSF
SC
QSF
SC
QSF
CASE II
CASE III
Tap1
(low)
Bit
127
Tap1
(high)
Bit
255
Tap2
(low)
Bit
127
Tap1
(low)
Row
Tap1
(high)
Row
Tap2
(low)
Row
Tap2
(high)
Row
Tap1
(low)
Tap2
(low)
Bit
127
Bit
255
Bit
127
Tap1
(low)
Tap2
(low)
Bit
127
Bit
255
Bit
127
Tap1
(high)
Tap1
(high)
Full-Register-Transfer Read
Split Register to the
High Half of the
Data Register
Split Register to the
Low Half of the
Data Register
Split Register to the
High Half of the
Data Register
NOTES: A. To achieve proper split-register operation, a full-register-transfer read should be performed before the first split-register-transfer
cycle. This is necessary to initialize the data register and the starting tap location. First serial access can begin after the
full-register-transfer read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first
split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register-transfer read cycle
and the first split-register cycle.
B. A split-register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the
rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the
inactive half. After the td(MSRL) is met, the split-register transfer into the inactive half must also satisfy the minimum td(RHMS)
requirement. td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register-transfer cycle into the inactive
half and the rising edge of the serial clock of the last bit (bit 127 or 255).
Figure 50. Split-Register Operating Sequence
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