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| 型號： | SMJ55166 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 54/62頁 |
| 文件大?。?/td> | 1403K |
| 代理商： | SMJ55166 |
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SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057C – APRIL 1995 – REVISED JUNE 1997
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
DSF
TRG
WEx
SC
A0–A8
SE
Row
SQ
H
L
Old Data
Old Data
Old Data
New Data
tc(TRD)
td(RLCL)
tw(RL)
td(RLCH)
tw(CL)
th(RLCA)
tsu(RA)
th(RA)
tsu(CA)
th(CLCA)
tsu(SFR)
tsu(TRG)
tsu(WMR)
th(RWM)
td(THRH)
td(THRL)
td(THSC)
tw(SCH)
ta(SQ)
th(SHSQ)
tc(SC)
ta(SQ)
th(SHSQ)
tw(RH)
td(RLTH)
tw(SCL)
td(SCTR)
td(CHRL)
QSF
Tap Point Bit A7
td(GHQSF)
td(RLQSF)
td(CLQSF)
DQ0–DQ15
Hi-Z
tw(GH)
th(SFR)
td(CLTH)
td(CAGH)
Tap Point
A0–A8
td(RLCA)
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written
into from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., the SQ is enabled), allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive
transition of SC.
C. A0–A7: register tap point; A8: identifies the DRAM row half
D. Late load operation is defined as td(THRH) < 0 ns.
Figure 46. Full-Register-Transfer Read Timing, Real-Time Load Operation/Late-Load Operation
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