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| 型號： | SMJ55166 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 49/62頁 |
| 文件大?。?/td> | 1403K |
| 代理商： | SMJ55166 |
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SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057C – APRIL 1995 – REVISED JUNE 1997
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A8
WEx
TRG
DSF
DQ0–DQ15
tw(RL)P
td(RLCH)
td(RLCL)
tw(CL)
tw(CH)
tc(P)
td(CLRH)
td(CHRL)
tw(RH)
tsu(RA)
th(RA)
tsu(CA)
th(CLCA)
td(CARH)
1
tsu(WMR)
th(RWM)
tsu(SFR)
th(SFR)
th(SFC)
tsu(SFC)
th(SFC)
tsu(WCH)
tw(WL)
tsu(WCH)
tsu(WRH)
tsu(DQR)
th(RDQ)
tsu(DWL)
tsu(DCL)
th(CLD)
th(WLD)
th(RLD)
Row
Block Address
A2–A8
2
3
3
Block Address
A2–A8
th(TRG)
tsu(TRG)
See Note A
td(RLCA)
td(CHRL)
th(RLCA)
tsu(SFC)
td(CACH)
Referenced to the first falling edge of WEx or the falling edge of CAS, whichever occurs later
NOTE A: To assure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late-write feature is used.
If the early write-cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling edge of RAS.
Figure 41. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 13. Enhanced-Page-Mode Block-Write-Cycle State Table
CYCLE
STATE
2
1
3
Block-write operation (nonmasked)
H
Don’t care
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don’t care
Column mask
Write-mask data
0: I/O write disable
1: I/O write enable
Example:
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column-mask data DQi – DQi + 3
0: column write disable
1: column write enable
(i = 0, 4, 8, 12)
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