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參數(shù)資料
| 型號： | SMJ55166 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內存 |
| 文件頁數(shù)： | 11/62頁 |
| 文件大小： | 1403K |
| 代理商： | SMJ55166 |
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SMJ55166
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS057C – APRIL 1995 – REVISED JUNE 1997
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
functional operation description
Table 3. DRAM Function Table
RAS FALL
CAS
FALL
ADDRESS
DQ0–DQ15
MNE
CODE
FUNCTION
CAS
TRG
WEx
DSF
DSF
RAS
CAS§
RAS
WEL
WEU
CAS
Reserved (do not use)
L
L
L
L
X
X
X
X
X
—
CBR refresh (no reset) and stop-point
set (CBRS)
CBR refresh (option reset)||
L
X
L
H
X
Stop
Point#
X
X
X
CBRS
L
X
H
L
X
X
X
X
X
CBR
CBR refresh (no reset)
L
X
H
H
X
X
X
X
X
CBRN
DRAM write
(nonpersistent write-per-bit)
H
H
L
L
L
Row
Address
Column
Address
Write
Mask
Valid
Data
RWM
DRAM block write
(nonpersistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A2–A8
Write
Mask
Column
Mask
BWM
DRAM write
(persistent write-per-bit)
H
H
L
L
L
Row
Address
Column
Address
X
Valid
Data
RWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A2–A8
X
Column
Mask
BWM
DRAM write (nonmasked)
H
H
H
L
L
Row
Address
Column
Address
X
Valid
Data
RW
DRAM block write (nonmasked)
H
H
H
L
H
Row
Address
Block
Address
A2–A8
X
Column
Mask
BW
Load write-mask register
H
H
H
H
L
Refresh
Address
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Address
X
X
Color
Data
LCR
Legend:
Col Mask
Write Mask
X
DQ0–DQ15 are latched on either the first falling edge of WEx or the falling edge of CAS, whichever occurs later.
Logic L is selected when either or both WEL and WEU are low.
§The column address and block address are latched on the first falling edge of CAS.
CBRS cycle should be performed immediately after the power-up initialization cycle.
#A0–A3, A8: don’t care; A4–A7 : stop-point code
||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
=
=
=
H: Write to address/column enabled
H: Write to I/O enabled
Don’t care
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