參數(shù)資料
型號(hào)： SMJ55161
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 16-BIT MULTIPORT VIDEO RAM
中文描述： 262144由16位多端口視頻內(nèi)存
文件頁(yè)數(shù)： 43/64頁(yè)
文件大?。?/td> 1505K
代理商： SMJ55161
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
tsu(TRG)
td(CLGH)
RAS
CASx
A0–A8
WE
TRG
DSF
DQ0–
DQ15
tw(RL)P
tw(RH)
td(RLCL)
tw(CL)
tw(CH)
td(CLRH)
td(CHRL)
td(RLCH)
th(RA)
th(RLCA)
th(CLCA)
tc(P)
td(CARH)
th(TRG)
tsu(WMR)
tsu(rd)
ta(G)
ta(R)
(see Note B)
ta(CA)
(see Note A)
ta(CP)
(see Note A)
tdis(G)
Row
Column
Column
Data Out
ta(C)
Data In
td(DCL)
td(DGL)
tt
ta(CA)
th(RHrd)
td(RLCA)
tsu(RA)
tsu(CA)
th(SFR)
tsu(SFR)
Data Out
td(CACH)
tdis(RH)
th(CLQ)
tdis(WL)
NOTES: A. Access time is ta(CP) or ta(CA) dependent.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CASx to select the desired
write mode (normal, block write, etc.).
Figure 34. Enhanced-Page-Mode Read-Cycle Timing
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