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參數(shù)資料
| 型號(hào)： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 4/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description
The SMJ55161 multiport-video random-access memory (RAM) is a high-speed, dual-port memory device. It
consists of a dynamic RAM (DRAM) module organized as 262 144 words of 16 bits each interfaced to a
serial-data register (serial-access memory [SAM]) organized as 256 words of 16 bits each. The SMJ55161
supports three basic types of operation: random access to and from the DRAM, serial access from the serial
register, and transfer of data from any row in the DRAM to the serial register. Except during transfer operations,
the SMJ55161 can be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The SMJ55161 is equipped with several features designed to provide higher system-level bandwidth and to
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel-draw rates are
achieved by the device’s (4
×
4)
×
4 block-write feature. The block-write mode allows 16 bits of data (present
in an on-chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 64 bits of data can be written to memory during each CAS cycle time. Also, on the DRAM port, a
write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent
write cycles without reloading. The SMJ55161 also offers byte control which can be applied in read cycles, write
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The SMJ55161 also
offers extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and standard
DRAM cycles.
The SMJ55161 offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port)
that enables real-time-register-load implementation for continuous serial-data streams without critical timing
requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM
port, the other half can be loaded from the memory array. For applications not requiring real-time register load
(for example, loads done during CRT-retrace periods), the full-register mode of operation is retained to simplify
system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 45 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
output, QSF, is included to indicate which half of the serial register is active.
All inputs, outputs, and clock signals on the SMJ55161 are compatible with Series 74 TTL. All address lines and
data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater
system flexibility.
The SMJ55161 is offered in a 68-pin ceramic pin-grid-array package (GB suffix) and a 64-pin ceramic flatpack
(HKC suffix).
The SMJ55161 and other TI multiport-video RAMs are supported by a broad line of graphic processors and
control devices from TI. See Table 2 and Table 4 for additional information.
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