參數(shù)資料
型號(hào)： SMJ55161
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 16-BIT MULTIPORT VIDEO RAM
中文描述： 262144由16位多端口視頻內(nèi)存
文件頁(yè)數(shù)： 30/64頁(yè)
文件大小： 1505K
代理商： SMJ55161
SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
256-/512-bit compatibility of split-register programmable stop point
The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the
CBRS cycle is initiated, the stop-point mode becomes active. In stop-point mode only, column-address bits AY7
and AY8 are internally swapped to assure compatibility (see Figure 26). This address-bit swap applies to the
column address and is effective for all DRAM and transfer cycles. For example, during the split-register-transfer
cycle with stop point, column-address bit AY8 is a don’t care and AY7 decodes the DRAM half-row for the
split-register transfer. During stop-point mode, a CBR (option reset) cycle is not recommended because this
ends the stop-point mode and restores address bits AY7 and AY8 to their normal functions. Consistent use of
CBR cycles ensures that the SMJ55161 remains in normal mode.
512
×
512
Memory Array
256-Bit
Data Register
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1
0
255
AY8 = 0
AY8 = 1
512
×
512
Memory Array
256-Bit
Data Register
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1
0
255
AY8 = 0
AY8 = 1
NONSTOP-POINT MODE
STOP-POINT MODE
Figure 26. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point
IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately
after the power-up initialization cycles are performed.
power up
To achieve proper device operation, an initial pause of 200
μ
s is required after power up followed by a minimum
of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer-read cycle and two
SC cycles are required to initialize the SAM port.
After initialization, the internal state of the SMJ55161 is as shown in Table 6.
Table 6. Internal State of SMJ55161
STATE AFTER INITIALIZATION
QSF
Write mode
Write-mask register
Color register
Serial-register tap point
SAM port
Defined by the transfer cycle during initialization
Nonpersistent mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
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