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參數(shù)資料
| 型號(hào)： | SMJ55161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 16-BIT MULTIPORT VIDEO RAM |
| 中文描述： | 262144由16位多端口視頻內(nèi)存 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | SMJ55161 |
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SMJ55161
262144 BY 16-BIT
MULTIPORT VIDEO RAM
SGMS056D – MAY 1995 – REVISED OCTOBER 1997
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
full-register-transfer read
A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TRG
is brought low and latched at the falling edge of RAS. Nine row-address bits (A0–A8) are also latched at the
falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits
(A0– A8) are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is
transferred. Address bits A0–A7 select one of the SAM’s 256 available tap points from which the serial data
is read out (see Figure 15).
512
×
512
Memory Array
256-Bit
Data Register
0
255 256
511
0
255
A8 = 0
A8 = 1
Figure 15. Full-Register-Transfer Read
A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late
load. Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer read cycle
(see Figure 16).
Early Load
Real-Time Load
Late Load
RAS
CASx
A0–A8
TRG
WE
Row
Tap
Point
Row
Tap
Point
Row
Tap
Point
SC
Tap
Bit
Tap
Bit
Tap
Bit
Old
Data
Old
Data
Old
Data
Old
Data
Old
Data
Figure 16. Example of Full-Register-Transfer Read Operations
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