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| 型號： | SMJ44C256 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 262144 4位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 323K |
| 代理商： | SMJ44C256 |
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
ALT.
’44C256-80
MIN
’44C256-10
MIN
’44C256-12
MIN
’44C256-15
MIN
UNIT
SYMBOL
MAX
MAX
MAX
MAX
ta(C)
ta(CA)
ta(RL)
ta(G)
Access time from CAS low
tCAC
tAA
tRAC
tGAC
20
25
30
40
ns
Access time from column-address
40
45
55
70
ns
Access time from RAS low
80
100
120
150
ns
Access time from G low
20
25
30
40
ns
ta(CP)
Access time from CAS high column
precharge
tCPA
40
50
60
75
ns
tdis(CH)
Output disable time after CAS high
(see Note 4)
tOFF
20
25
30
35
ns
tdis(G)
Output disable time after G high
(see Note 4)
NOTE 4: tdis(CH) and tdis(G) are specified when the output is no longer driven. The outputs are disabled by bringing either G or CAS high.
tGOFF
20
25
30
35
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
PARAMETER
ALT.
’44C256-80
MIN
’44C256-10
MIN
’44C256-12
MIN
’44C256-15
MIN
UNIT
SYMBOL
MAX
MAX
MAX
MAX
tc(rd)
tc(W)
Cycle time, read (see Note 6)
tRC
tWC
150
190
220
260
ns
Cycle time, write
150
190
220
260
ns
tc(rdW)
Cycle time,read-write/read-
modify-write
tRWC
225
270
305
355
ns
tc(P)
Cycle time, page-mode read
or write (see Note 7)
tPC
50
55
65
80
ns
tc(PM)
Cycle time, page-mode read-
modify-write
tPRWC
115
135
150
175
ns
tw(CH)
Pulse duration, CAS high
tCP
10
10
15
25
ns
tw(CL)
Pulse duration, CAS low
(see Note 8)
tCAS
20
10 000
25
10 000
30
10 000
40
10 000
ns
tw(RH)
Pulse duration, RAS high
(precharge)
tRP
60
80
90
100
ns
tw(RL)
Pulse duration,
nonpage mode RAS low
(see Note 9)
tRAS
80
10 000
100
10 000
120
10 000
150
10 000
ns
tw(RL)P
Pulse duration,
page mode RAS low
(see Note 9)
tRASP
80
100 000
100
100 000
120
100 000
150
100 000
ns
tw(WL)
Pulse duration, write low
tWP
15
15
20
25
ns
tsu(CA)
Setup time, column address
before CAS low
5. Timing measurements in this table are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
7. To assure tc(P) min, tsu(CA) should be
≥
tw(CH).
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this can require
additional CAS low time [tw(CL)].
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this can require
additional RAS low time [tw(RL)].
tASC
5
5
5
5
ns
NOTES:
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