參數(shù)資料
型號(hào)： SMJ44C256
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
中文描述： 262144 4位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 323K
代理商： SMJ44C256
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
functional block diagram
Row
Address
Buffers
(9)
Column
Address
Buffers
(9)
A0
A1
A2
A3
A4
A5
A6
A7
A8
256K
Array
Row
Decode
256K
Array
256K
Array
Row
Decode
256K
Array
Column Decode
I/O
Buffers
4 of 8
Selection
Data
In
Reg
Data
Out
Reg
DQ1–DQ4
4
4
4
RAS
CAS
W
G
Sense Amplifiers
Sense Amplifiers
Timing and Control
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the CAS page cycle
time used. With minimum CAS page cycle time, all 512 columns specified by column addresses A0 through A8
can be accessed without intervening RAS cycles.
Unlike conventional page mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The column address
latches to the first CAS falling edge. This feature allows the SMJ44C256 to operate at a wider data bandwidth
than conventional page mode parts, since data retrieval begins as soon as column address is valid rather than
when CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column
address can be presented immediately after t
h(RA)
(row address hold time) has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after t
a(C)
maximum (access time from CAS
low), if t
a(CA)
maximum (access time from column address) has been satisfied. In the event that column
addresses for the next page cycle are valid at the time CAS goes high, access time for the next cycle is
determined by the later occurrence of t
a(C)
or t
a(CP)
(access time from rising edge of CAS).
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SML-010DT Chip LEDs with reflectors
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