參數(shù)資料
型號(hào)： SMJ44C256
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
中文描述： 262144 4位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù)： 16/21頁(yè)
文件大?。?/td> 323K
代理商： SMJ44C256
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
See Note A
RAS
CAS
A0–A8
W
DQ1–DQ4
G
Column
tw(RL)P
Column
Row
Valid
Out
tw(RH)
td(CHRL)
td(CLRH)
tw(CH)
td(RLCH)
tw(CL)
td(RLCL)
tsu(RA)
th(CA)
td(CLWL)
td(CAWL)
td(RLWL)
tw(WL)
tsu(WCH)
tsu(WRH)
th(RA)
ta(C)
ta(CP)
tdis(G)
td(GHD)
ta(G)
ta(CA)
ta(R)
tsu(D)
Valid In
Valid Out
See Note A
th(D)
td(RLCA)
tsu(CA)
tc(PM)
tsu(rd)
th(RLCA)
th(WLGL)
th(WLGL)
Don’t Care
Don’t Care
Don’t Care
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing (see Note B)
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