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參數(shù)資料
| 型號： | SMJ418160 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576由16位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 356K |
| 代理商： | SMJ418160 |
SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
data in (DQ0–DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first xCAS occurrence with setup and hold times referenced to this signal. In
a delayed-write or read-modify-write cycle, xCAS is low already and the data is strobed in by W with setup and
hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (DQ0–DQ15)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access-time interval t
CAC
. t
CAC
begins with
the negative transition of xCAS as long as t
RAC
and t
AA
are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh ’416160
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 4096 rows (A0–A11). A normal-read or -write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
RAS-only refresh ’418160
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 1024 rows (A0–A9). A normal-read or -write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter t
CSR
) and holding
it low after RAS falls (see parameter t
CHR
). For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after power up to the full V
CC
level. These eight initialization cycles must include at least one refresh
(RAS-only or xCBR) cycle.
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