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| 型號： | SMJ418160 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576由16位動態(tài)隨機(jī)存取存儲器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 356K |
| 代理商： | SMJ418160 |
SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
UCAS
Address
W
OE
Column
tRASP
Column
Row
Valid Out
tOEA
Valid In
Valid In
Valid Out
tRP
tCRP
tRSH
tCP
tCSH
tPRWC
tCAS
tRCD
tASR
tASC
tCAH
tCWD
tAWD
tRWD
tCWL
tRWL
tRAH
tCAC
tCPA
(see Note B)
tOEH
tOED
tOEH
tOEZ
tAA
tRAC
tRCS
(see Note C)
tDS
LCAS
tCLCH
(see Note A)
tRAD
DQ0–DQ15
tWP
tAA
tDH
tCPW
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Access time is tCPA- or tAA-dependent.
C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
D. xCAS order is arbitrary.
E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are
not violated.
F. tCAC is measured from xCAS to its corresponding DQx.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
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