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參數(shù)資料
| 型號： | SMJ418160 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576由16位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 356K |
| 代理商： | SMJ418160 |
SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
UCAS
LCAS
Address
W
DQ8–DQ15
OE
tRWC
Don’t Care
Column
Row
Valid Out
tRAS
tRP
tRCD
tT
tCP
tRAD
tRAH
tCAH
tAWD
tCWD
tCWL
tRCS
tWP
tRWD
tCAC
tRAC
tOEA
tOED
Valid In
tAA
DQ0–DQ7
Valid Out
tDH
Don’t Care
Don’t Care
Don’t Care
tASR
tCAS
tRWL
tCSH
tRSH
tASC
tCLCH
(see Note A)
tOEZ
Don’t Care
tDS
tCRP
See Note B
See Note B
Don’t Care
(see Note C)
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. tCAC is measured from xCAS to its corresponding DQx.
D. xCAS order is arbitrary.
Figure 5. Read-Modify-Write-Cycle Timing
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