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SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SMJ418160
PARAMETER
TEST CONDITIONS
’418160-70
MIN
’418160-80
MIN
UNIT
MAX
MAX
VOH
High-level output
voltage
IOH = – 5 mA
2.4
2.4
V
VOL
Low-level output voltage
IOL = 4.2 mA
VCC = 5.5 V,
All others = 0 V to VCC
VCC = 5.5 V,
xCAS high
0.4
0.4
V
II
Input current (leakage)
VI = 0 V to 6.5 V,
±
10
±
10
μ
A
IO
Output current (leakage)
VO = 0 V to VCC,
±
10
±
10
μ
A
ICC1§
Read- or write-cycle current
VCC = 5.5 V,
VIH = 2.4 V (TTL),
After one memory cycle,
RAS and xCAS high
Minimum cycle
180
170
mA
ICC2
Standby current
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and xCAS high
1
1
mA
ICC3§
Average refresh current (RAS only refresh or
CBR)
VCC = 5.5 V,
RAS cycling,
xCAS high (RAS only),
RAS low after xCAS low (CBR)
VCC = 5.5 V,
RAS low,
Minimum cycle,
180
170
mA
ICC4
Average page current
tPC = MIN,
xCAS cycling
180
170
mA
ICC7
Standby current, outputs enabled
RAS = VIH,
Data out = enabled
xCAS = VIL,
5
5
mA
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
§Measured with a maximum of one address change while RAS = VIL
Measured with a maximum of one address change while xCAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
Ci(A)
Ci(OE)
Ci(RC)
Ci(W)
Co
#A10 and A11 are NC for SMJ418160.
NOTE 3: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25
°
C with a 1-MHz signal
applied to the pin under test. All other pins are open.
Input capacitance, A0–A11#
8
Input capacitance, OE
8
pF
Input capacitance, xCAS and RAS
8
pF
Input capacitance, W
8
pF
Output capacitance
10
pF