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參數(shù)資料
| 型號(hào)： | SMJ416160 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576由16位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 356K |
| 代理商： | SMJ416160 |
SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
dual CAS
Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins
(DQ0–DQ15), with LCAS corresponding to DQ0–DQ7 and UCAS corresponding to DQ8–DQ15. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its
corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge.
All address-setup and -hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter t
CAC
) is measured from each individual xCAS to its corresponding DQx pin.
In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time
(see parameter t
CP
) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, t
CLCH
. During t
CLCH
, at
least one xCAS must be brought low before the other xCAS is taken high.
For early-write cycles, the data is latched on the first xCAS falling edge. Only the DQs that have the
corresponding xCAS low are written into. Each xCAS must meet t
CAS
minimum in order to ensure writing
into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet t
CP
.
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without
intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the device to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather
than when xCAS goes low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time (t
RAH
) has been satisfied, usually
well in advance of the falling edge of xCAS. In this case, data is obtained after access time from xCAS low (t
CAC
)
maximum if access time from column address (t
AA
) maximum has been satisfied. In the event that column
addresses for the next page cycle are valid at the time xCAS goes high, minimum-access time for the next cycle
is determined by access time from rising edge of the last xCAS (t
CPA
).
address: A0–A11 (’416160) and A0–A9 (’418160)
Twenty address bits are required to decode one of the 1048576 storage-cell locations. For the SMJ416160,
12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits
are set up on A0 through A7 and latched onto the chip by the first xCAS. For the SMJ418160, ten row-address
bits are set up on A0–A9 and latched onto the chip by RAS. Ten column-address bits are set up on A0–A9 and
latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and
xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS
is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ416400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| SMJ4164-12FGE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Page Mode DRAM |
| SMJ4164-12FGS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SMJ4164-12JDE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Page Mode DRAM |
| SMJ4164-15FGE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Page Mode DRAM |
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