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參數(shù)資料
| 型號： | SMJ416160 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576由16位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 356K |
| 代理商： | SMJ416160 |
SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Don’t
Care
Valid
Out
Valid
Out
Valid
Out
RAS
UCAS
Address
W
DQ8–DQ15
DQ0–DQ7
OE
Column
Column
tRASP
tRCD
tRP
tRSH
tPC
tCP
tASR
tRAH
tASC
tCAH
tCAL
tRAL
tRAD
tRCH
tRRH
tOEZ
tRCS
tAA
tRAC
tAA
tOEA
LCAS
Row
Don’t Care
tCAC
(see Note B)
Don’t
Care
tCPA
tCAS
tRHCP
tCLCH
(see Note A)
(see Note C)
See Note D
See Note D
tOEA
tOFF
Don’t Care
Don’t Care
Don’t Care
tCSH
tCRP
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. tCAC is measured from xCAS to its corresponding DQx.
C. Access time is tCPA- or tAA-dependent.
D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing
specifications are not violated.
F. xCAS order is arbitrary.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
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