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參數(shù)資料
| 型號(hào)： | SMJ320C6201BGLP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 56/73頁(yè) |
| 文件大?。?/td> | 1093K |
| 代理商： | SMJ320C6201BGLP |
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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
56
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 33)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
4*
MAX
MIN
MAX
1
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
4
ns
2
Hold time, FSR high after CLKS high
4*
4
ns
*This parameter is not production tested.
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
Figure 33. FSR Timing When GSYNC = 1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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