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| 型號： | SMJ320C6201BGLP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 50/73頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | SMJ320C6201BGLP |
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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles
(see Figure 28, Figure 29, Figure 30, and
Figure 31)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
1
tsu(SEL-HSTBL)
th(HSTBL-SEL)
Setup time, select signals valid before HSTROBE low
Hold time, select signals valid after HSTROBE low
1
1
ns
2
2
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
2
2
CLKOUT1
cycles
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive
accesses
Setup time, select signals valid before HAS low
Hold time, select signals valid after HAS low
2*
2
CLKOUT1
cycles
10
tsu(SEL-HASL)
th(HASL-SEL)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
1
1
ns
11
2
2
ns
12
Setup time, host data valid before HSTROBE high
1
1
ns
13
Hold time, host data valid after HSTROBE high
1
1
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE
should not be inactivated until HRDY is active (low);
otherwise, HPI writes will not complete properly.
1*
1
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
*This parameter is not production tested.
switching characteristics during host-port interface cycles
§
(see Figure 28, Figure 29, Figure 30,
and Figure 31)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
5
td(HCS-HRDY)
td(HSTBL-HRDYH)
Delay time, HCS to HRDY
Delay time, HSTROBE low to HRDY high#
1*
7*
1
7
ns
6
3*
12*
3
12
ns
7
toh(HSTBL-HDLZ)
Output hold time, HD low impedance after HSTROBE low
for an HPI read
4*
4
ns
8
td(HDV-HRDYL)
toh(HSTBH-HDV)
td(HSTBH-HDHZ)
td(HSTBL-HDV)
td(HSTBH-HRDYH)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
§The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
*This parameter is not production tested.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
||This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
Delay time, HD valid to HRDY low
P – 3*
P*
P – 2
P
ns
9
Output hold time, HD valid after HSTROBE high
3*
12*
3
12
ns
15
Delay time, HSTROBE high to HD high impedance
3*
12*
3
12
ns
16
Delay time, HSTROBE low to HD valid
Delay time, HSTROBE high to HRDY high||
3*
12*
3
12
ns
17
3*
12*
3
12
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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