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參數(shù)資料
| 型號(hào)： | SMJ320C6201BGLP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 46/73頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | SMJ320C6201BGLP |
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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles
(see Figure 25)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
5*
MAX
MIN
MAX
1
tsu(HOLDH-CKO1H)
th(CKO1H-HOLDL)
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
*This parameter is not production tested.
Setup time, HOLD high before CLKOUT1 high
1
ns
2
Hold time, HOLD low after CLKOUT1 high
2*
4
ns
switching characteristics for the HOLD/HOLDA cycles (see Figure 25)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
3
tR(HOLDL-BHZ)
Response time, HOLD low to EMIF Bus high impedance
4*
4
CLKOUT1
cycles
4
tR(BHZ-HOLDAL)
Response time, EMIF Bus high impedance to HOLDA low
1*
2*
1
2
CLKOUT1
cycles
5
tR(HOLDH-HOLDAH) Response time, HOLD high to HOLDA high
4*
6
4
7
CLKOUT1
cycles
6
td(CKO1H-HOLDAL)
td(CKO1H-BHZ)
td(CKO1H-BLZ)
Delay time, CLKOUT1 high to HOLDA valid
Delay time, CLKOUT1 high to EMIF Bus high impedance§
Delay time, CLKOUT1 high to EMIF Bus low impedance§
–1*
5
1
8
ns
7
–1*
5*
3
11
ns
8
–1*
5*
3
11
ns
9
tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance
3*
5*
3
6
CLKOUT1
cycles
*This parameter is not production tested.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
§EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus
External Requester
DSP Owns Bus
’C62x
Ext Req
’C62x
8
7
3
4
6
6
1
2
CLKOUT1
HOLD
HOLDA
EMIF Bus
1
5
9
2
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 25. HOLD/HOLDA Timing
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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