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參數(shù)資料
| 型號： | SMJ320C6201BGLP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 22/73頁 |
| 文件大小： | 1093K |
| 代理商： | SMJ320C6201BGLP |
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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock PLL (continued)
Table 1. SM320C6201 PLL Component Selection Table
CYCLE
TIME (ns)
CLKMODE
CLKIN
(MHz)
CLKOUT1
(MHz)
R1
(
)
C1
(
μ
F)
C2
(pF)
EMI FILTER
PART NO.
TYPICAL
LOCK TIME
(
μ
s)§
59
5
x4
50
200
16.9
0.15
2700
TDK #153
5.5
x4
45.5
181.8
13.7
0.18
3900
TDK #153
49
6
x4
41.6
166.7
17.4
0.15
3300
TDK #153
68
6.5
x4
38.5
153.8
16.2
0.18
3900
TDK #153
70
7
x4
35.7
142.9
15
0.22
3900
TDK #153
72
7.5
x4
33.3
133.3
16.2
0.22
3900
TDK #153
84
8
x4
31.3
125
14
0.27
4700
TDK #153
77
8.5
x4
29.4
117.7
11.8
0.33
6800
TDK #153
67
9
x4
27.7
111.1
11
0.39
6800
TDK #153
68
9.5
x4
26.3
105.3
10.5
0.39
8200
TDK #153
65
10
x4
25
100
10
0.47
8200
TDK #153
68
For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be
connected to a clean supply and the PLLG and PLLF terminals should be tied together.
F
ull
EMI filter part number : ACF 451832-153-T
§Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
Table 2. SM320C6201B PLL Component Selection Table
CLKMODE
R1
(
)
C1
(nF)
C2
(pF)
EMI FILTER
PART NO.
TYPICAL
LOCK TIME (
μ
s)§
x4
60.4
27
560
TDK #153
75
For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be
connected to a clean supply and the PLLG and PLLF terminals should be tied together.
F
ull
EMI filter part number : ACF 451832-153-T
§Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
power supply sequencing
For the ’C6201 device, the 2.5-V supply powers the core and the 3.3-V supply powers the I/O buffers. For the
’C6201B device, the 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply
should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O buffers have
valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other
chips on the board.
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